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Data Sheet-sram/62256ald1
http://www.hea.com/hean2/sram/62256ald1.htm
HY62256A-(I) Series
32Kx8bit CMOS SRAM
Description Features The Fully static operation and HY62256A/HY62256A-I Tri-state outputs is a high-speed, low TTL compatible inputs power and 32,786 x 8-bits and outputs CMOS Static Random Low power consumption Access Memory -2.0V(min.) data fabricated using retention Hyundai's high Standard pin performance CMOS configuration process technology. The -28 pin 600 mil PDIP HY62256A/HY62256A-I -28 pin 330 mil SOP has a data retention mode -28 pin 8x13.4 mm that guarantees data to TSOP-1 remain valid at the (standard and reversed) minimum power supply voltage of 2.0 volt. Using the CMOS technology, supply voltages from 2.0 to 5.5 volt has little effect on supply current in the data retention mode. The HY62256A/HY62256A-I is suitable for use in low voltage operation and battery back-up application.
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Data Sheet-sram/62256ald1
http://www.hea.com/hean2/sram/62256ald1.htm
Voltage Speed Product No. (V) (ns) HY62256A 5.0
Standby Operation Current(uA) Temperature Current(mA) (C) L LL 1mA 100 25 0-70(Normal) 1mA 100 -40-85(E.T.)
55/70/85 50 55/70/85 50
HY62256A-I 5.0
Note 1. E T. Extended Temperature, Normal: Normal Temperature 2. Current value is max. Features | Pins | Ratings | Timing | Package | Ordering
3101 North First Street, San Jose, CA 95134 Phone: 408-232-8000 URL: http://www.hea.com/
SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com
Copyright (c) 1997 Hyundai Electronics America.
2 of 2
22/10/97 12:30
-sram/62256alp1
http://www.hea.com/hean2/sram/62256alp1.htm
HYUNDAI ELECTRONICS AMERICA HY62256A-(I) Series 32Kx8bit CMOS SRAM PIN CONNECTION
PIN INFORMATION
BLOCK DIAGRAM
PIN DESCRIPTION Pin Name /CS /WE /OE A0-A14 I/O1-I/O8 Vcc Vss Chip Select Write Enable Output Enable Address Inputs Data Input/Output Power(+5.0V) Ground Features | Pins | Ratings | Timing | Package | Ordering
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Pin Function
3101 North First Street, San Jose, CA 95134
22/10/97 12:32
-sram/62256alp1
http://www.hea.com/hean2/sram/62256alp1.htm
Phone: 408-232-8000 URL: http://www.hea.com/
SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com
Copyright (c) 1997 Hyundai Electronics America.
2 of 2
22/10/97 12:32
-sram/62256ala1
http://www.hea.com/hean2/sram/62256ala1.htm
HYUNDAI ELECTRONICS AMERICA HY62256A-(I) Series 32Kx8bit CMOS SRAM ABSOLUTE MAXIMUM RATING (1) Symbol VCC VIN VOUT TA TSTG PD IOUT TSOLDER Note Parameter
RATINGS INFORMATION
Rating
Unit
Remark
Power Supply Input/Output -0.5 to 7.0 V Voltage Operating Temperature Storage Temperature Power Dissipation Data OutPut Current 0 to 70 -40 to 85 1.0 50 C C W mA C / sec HY62256A HY62256A-I
-65 to 150 C
Lead Soldering Temperature 260 /10 & Time
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS TA=0C to 70C / TA= -40C to 85C (E.T.) Symbol VCC VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Min 4.5 2.2 -0.5(1) Typ 5.0 5.5 VCC+0.5 0.8 Max Unit V V V
Note 1. VIL = -3.0V for pulse width less than 30ns
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-sram/62256ala1
http://www.hea.com/hean2/sram/62256ala1.htm
TRUTH TABLE /CS H L L L /WE X H H L /OE X H L X Standby Output Disabled Read Write MODE I/O OPERATION High-Z High-Z Data Out Data In
Note: 1. H=VIH, L=VIL, X=Don't Care Features | Pins | Ratings | Timing | Package | Ordering DC CHARACTERISTICS Vcc = 5V ?% TA = 0C to 70C (Normal) / -40C to 85C (E.T.) unless otherwise specified Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition Vss <= VIN <= Vcc Min Typ Max Unit -1 1 1 uA uA
Vss <= VOUT <= Vcc /CS=VIH or -1 /OE=VIH or /WE = VIL /CS= VIL, VIN=VIH or VIL, II/O= 0mA /CS = VIL Min. Duty Cycle = 100%, II/O =0mA -
Icc
Operating Power Supply Current Average Operating Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Input) HY62256A
30
50
mA
Icc1 ISB
40 0.4 2 1 2 -
70 2 1 100 25 1 100 0.4 -
mA mA mA uA uA mA uA V V
/CS = VIH VIN = VIH or VIL /CS >= VccL 0.2V VIN <= 0.2V or LL VIN >= VCC-0.2V L IOL= 2.1 mA IOH = 1mA 2.4
ISB1
HY62256A-I
VOL VOH
Output Low Voltage Output High Voltage
Note: Typical values are at Vcc = 5.0V TA = 25C
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-sram/62256ala1
http://www.hea.com/hean2/sram/62256ala1.htm
AC CHARACTERISTICS Vcc = 5V()10%, TA = 0C to 70C (Normal)/ -40C to 85C (E.T.) unless otherwise specified. # Symbol READ CYCLE 1 tRC 2 tAA 3 tACS 4 tOE 5 tCLZ 6 tOLZ 7 tCHZ 8 tOHZ 9 tOH Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Out Disable to Output in High Z Output Hold from Address Change Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Write to Output in High Z 55 5 5 0 0 5 55 55 30 20 20 70 5 5 0 0 5 70 70 35 30 30 85 5 5 0 0 5 85 85 45 30 30 ns ns ns ns ns ns ns ns ns Parameter -55 -70 -85 Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE 10 tWC 11 tCW 12 tAW 13 tAS 14 tWP 15 tWR 16 tWHZ 17 tDW 18 tDH 19 tOW 55 50 50 0 40 0 0 20 70 65 65 0 50 0 0 35 0 5 30 85 75 75 0 55 0 0 40 0 5 30 ns ns ns ns ns ns ns ns ns ns
Data to Write Time Overlap 25 Data Hold from Write Time 0 Output Active from End of Write 5
AC TEST CONDITIONS TA = 0C to 70C (Normal) / -40C to 85C (E.T.) unless otherwise specified. PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load
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VALUE 0.8V to 2.4V 5ns 1.5V CL = 100pF + 1TTL Load CL = 50pF + 1TTL Load
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70/85/100ns 55ns
-sram/62256ala1
http://www.hea.com/hean2/sram/62256ala1.htm
AC TEST LOADS
Note: Including jig and scope capacitance CAPACITANCE TAA= 25 C, f = 1.0MHz Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Condition VIN = 0V VI/O= 0V 6 8 Max Unit pF pF
Note: These parameters are sampled and not 100% tested Features | Pins | Ratings | Timing | Package | Ordering
3101 North First Street, San Jose, CA 95134 Phone: 408-232-8000 URL: http://www.hea.com/
SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com
Copyright (c) 1997 Hyundai Electronics America.
4 of 4
22/10/97 12:33
-sram/62256alt1
http://www.hea.com/hean2/sram/62256alt1.htm
HYUNDAI ELECTRONICS AMERICA HY62256A-I 32K x 8bit CMOS SRAM TIMING DIAGRAM READ CYCLE 1
TIMING INFORMATION
Note (READ CYCLE): 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for the read cycle. READ CYCLE 2
Note (READ CYCLE): 1. /WE is high for the read cycle. 2. Device is continuously selected /CS= VIL. 3. /OE =VIL. WRITE CYCLE 1 (/OE Clocked)
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-sram/62256alt1
http://www.hea.com/hean2/sram/62256alt1.htm
WRITE CYCLE 2 (/OE Low Fixed)
Notes (WRlTE CYCLE): 1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tcw is measured from the later of /CS going low to the end of write . 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS, or /WE going high. 5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state, input of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high impedance state. 7. DOUT is the same phase of latest written data in this write cycle. 8. DOUT is the read data of the new address.
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-sram/62256alt1
http://www.hea.com/hean2/sram/62256alt1.htm
DATA RETENTION CHARACTERISTIC TA= 0C to 70C (normal) /-40C to 85C (E.T.) Symbol VDR Parameter Vcc for Data Re! ention Test Condition /CS >= Vcc-0.2V Vss <= VIN <= Vcc Vcc = 3.0V /CS >= Vcc -0.2V Vss <= VIN <= Vcc L LL L Min Typ Max Unit 2 1 1 1 50 V uA
ICCDR
Data Retention Current
HY62256A HY62256A-1
15(2) uA 50 uA ns ns
tCDR tR
Chip Disable to Data Retention See Data 0 Time Retention Timing Diagram Operating Recovery Time tRC(3) -
Notes 1. Typical values are under the condition of TA = 25C 2. 3uA max. at TA= 0C to 40C 3. tRC is read cycle time. Data Retention Timing Diagram
RELIABILITY SPEC. TEST MODE ESD LATCH-UP HBM MM >= 2000V >= 250V <= -100mA >= 100mA Features | Pins | Ratings | Timing | Package | Ordering
3101 North First Street, San Jose, CA 95134 Phone: 408-232-8000 URL: http://www.hea.com/
TEST SPEC.
SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com
Copyright (c) 1997 Hyundai Electronics America.
3 of 3
22/10/97 12:35
-sram/62256alpk1
http://www.hea.com/hean2/sram/62256alpk1.htm
HYUNDAI ELECTRONICS AMERICA HY62256A-(I) Series 32Kx8bit CMOS SRAM 28pin 600mil Dual In-Line Package(P)
PACKAGE INFORMATION
28pin 330mil Small Outline Package(J)
28pin 8X13.4mm Thin Small Outline Package Standard(T1)
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-sram/62256alpk1
http://www.hea.com/hean2/sram/62256alpk1.htm
28pin 8X13.4mm Thin Small Outline Package SReversed(R1)
Features | Pins | Ratings | Timing | Package | Ordering
3101 North First Street, San Jose, CA 95134 Phone: 408-232-8000 URL: http://www.hea.com/
SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com
Copyright (c) 1997 Hyundai Electronics America.
2 of 2
22/10/97 12:37
-sram/62256alo1
http://www.hea.com/hean2/sram/62256alo1.htm
HYUNDAI ELECTRONICS AMERICA HY62256A-(I) Series 32Kx8bit CMOS SRAM Part No. HY62256AP HY62256ALP HY62256ALLP HY62256AJ HY62256ALJ HY62256ALLJ HY62256AT1 HY62256ALT1 HY62256ALLT1 HY62256AR1 HY62256ALR1 HY62256ALLR1 HY62256AP-I HY62256ALP-I HY62256AJ-I HY62256ALJ-I HY62256AT1-I HY62256ALT1-I HY62256AR2-I HY62256ALR2-I Speed 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 L-part L-part L-part L-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part Power
ORDERING INFORMATION
Temp. PDIP PDIP PDIP SOP SOP SOP
Package
TSOP-I Standard TSOP-I Standard TSOP-I Standard TSOP-I Reversed TSOP-I Reversed TSOP-I Reversed E.T. E.T. E.T. E.T. E .T. E.T. E.T. E.T. PDIP PDIP SOP SOP TSOP-I TSOP-I TSOP-I Reversed TSOP-I Reversed
Features | Pins | Ratings | Timing | Package | Ordering
3101 North First Street, San Jose, CA 95134 Phone: 408-232-8000 URL: http://www.hea.com/
SRAM Data Sheets | Memory Products | email: DRAMSRAMmemory@hea.com
Copyright (c) 1997 Hyundai Electronics America.
1 of 1
22/10/97 12:38

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